Specification Sheet

PCI Express* Controller (x4) Registers
500 Datasheet, Volume 2 of 2
14.31 Message Address (MA)—Offset 94h
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
15:8
0h
RO
Reserved (RSVD): Reserved.
7
0h
RO
B64AC: 64-bit Address Capable: Hardwired to 0 to indicate that the function does not
implement the upper 32 bits of the Message Address register and is incapable of
generating a 64-bit memory address.
This may need to change in future implementations when addressable system memory
exceeds the 32b/4GB limit.
6:4
0h
RW
MME: Multiple Message Enable: System software programs this field to indicate the
actual number of messages allocated to this device. This number will be equal to or
less than the number actually requested.
The encoding is the same as for the MMC field below.
3:1
0h
RO
MMC: Multiple Message Capable: System software reads this field to determine the
number of messages being requested by this device.
Value: Number of Messages Requested
000: 1
All of the following are reserved in this implementation:
001: 2
010: 4
011: 8
100: 16
101: 32
110: Reserved
111: Reserved
0
0h
RW
MSIEN: MSI Enable: Controls the ability of this device to generate MSIs.
0: MSI will not be generated.
1: MSI will be generated when we receive PME messages. INTA will not be generated
and INTA Status (PCISTS1[3]) will not be set.
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:2] + 94h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MA
FDWA
Bit
Range
Default &
Access
Field Name (ID): Description
31:2
0h
RW
MA: Message Address: Used by system software to assign an MSI address to the
device. The device handles an MSI by writing the padded contents of the MD register
to this address.
1:0
0h
RO
FDWA: Force DWord Align: Hardwired to 0 so that addresses assigned by system
software are always aligned on a DWord address boundary.