Specification Sheet
Datasheet, Volume 2 of 2 497
PCI Express* Controller (x4) Registers
14.27 Subsystem ID and Vendor ID Capabilities (SS)—
Offset 88h
This capability is used to uniquely identify the subsystem where the PCI device resides.
Because this device is an integrated part of the system and not an add-in device, it is
anticipated that this capability will never be used. However, it is necessary because
Microsoft will test for its presence.
Access Method
Default: 800Dh
3
1h
RO
NSR: No Soft Reset: No Soft Reset. When set to 1 this bit indicates that the device is
transitioning from D3hot to D0 because the power state commands do not perform a
internal reset. Config context is preserved. Upon transition no additional operating sys
intervention is required to preserve configuration context beyond writing the power
state bits.
When clear the devices do not perform an internal reset upon transitioning from D3hot
to D0 via software control of the power state bits.
Regardless of this bit the devices that transition from a D3hot to D0 by a system or
bus segment reset will return to the device state D0 uninitialized with only PME
context preserved if PME is supported and enabled.
2
0h
RO
Reserved (RSVD): Reserved.
1:0
0h
RO_V
PS: Power State: Indicates the current power state of this device and can be used to
set the device into a new power state. If software attempts to write an unsupported
state to this field, write operation should complete normally on the bus, but the data is
discarded and no state change occurs.
00: D0
01: D1 (Not supported in this device.)
10: D2 (Not supported in this device.)
11: D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI configuration
transactions (for power management control). This device also cannot generate
interrupts or respond to MMR cycles in the D3 state. The device should return to the
D0 state in order to be fully-functional.
When the Power State is other than D0, the bridge will Master Abort (i.e. not claim)
any downstream cycles (with exception of type 0 config cycles). Consequently, these
unclaimed cycles will go down DMI and come back up as Unsupported Requests, which
the Processor logs as Master Aborts in Device 0 PCISTS[13]
There is no additional hardware functionality required to support these Power States.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:2] + 88h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
RSVD
PNC
CID