Specification Sheet

Datasheet, Volume 2 of 2 495
PCI Express* Controller (x4) Registers
14.25 Power Management Capabilities (PM)—Offset 80h
Access Method
Default: C8039001h
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:2] + 80h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
PMES
D2PSS D1PSS
AUXC
DSI
APS
PMECLK
PCIPMCV
PNC
CID
Bit
Range
Default &
Access
Field Name (ID): Description
31:27
19h
RO
PMES: PME Support: This field indicates the power states in which this device may
indicate PME wake via PCI Express messaging. D0, D3hot & D3cold. This device is not
required to do anything to support D3hot & D3cold, it simply should report that those
states are supported. Refer to the PCI Power Management 1.1 specification for
encoding explanation and other power management details.
26
0h
RO
D2PSS: D2 Power State Support: Hardwired to 0 to indicate that the D2 power
management state is NOT supported.
25
0h
RO
D1PSS: D1 Power State Support: Hardwired to 0 to indicate that the D1 power
management state is NOT supported.
24:22
0h
RO
AUXC: Auxiliary Current: Hardwired to 0 to indicate that there are no 3.3Vaux
auxiliary current requirements.
21
0h
RO
DSI: Device Specific Initialization: Hardwired to 0 to indicate that special initialization
of this device is NOT required before generic class device driver is to use it.
20
0h
RO
APS: Auxiliary Power Source: Hardwired to 0.
19
0h
RO
PMECLK: PME Clock: Hardwired to 0 to indicate this device does NOT support PMEB
generation.
18:16
3h
RO
PCIPMCV: PCI PM CAP Version: Version - A value of 011b indicates that this function
complies with revision 1.2 of the PCI Power Management Interface Specification.
--Was Previously
Hardwired to 02h to indicate there are 4 bytes of power management registers
implemented and that this device complies with revision 1.1 of the PCI Power
Management Interface Specification.
15:8
90h
RO_V
PNC: Pointer to Next Capability: This contains a pointer to the next item in the
capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the capabilities
list is the Message Signaled Interrupts (MSI) capability at 90h. If MSICH (CAPL[0] @
7Fh) is 1, then the next item in the capabilities list is the PCI Express capability at A0h.
7:0
1h
RO
CID: Capability ID: Value of 01h identifies this linked list item (capability structure) as
being for PCI Power Management registers.