Specification Sheet

PCI Express* Controller (x4) Registers
494 Datasheet, Volume 2 of 2
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
DTSERRE
DTSTS
SDT
PDT
FB2BEN
SRESET
MAMODE
VGA16D
VGAEN
ISAEN
SERREN
PEREN
Bit
Range
Default &
Access
Field Name (ID): Description
15:12
0h
RO
Reserved (RSVD): Reserved.
11
0h
RO
DTSERRE: Discard Timer SERR# Enable: Not Applicable or Implemented. Hardwired
to 0.
10
0h
RO
DTSTS: Discard Timer Status: Not Applicable or Implemented. Hardwired to 0.
9
0h
RO
SDT: Secondary Discard Timer: Not Applicable or Implemented. Hardwired to 0.
8
0h
RO
PDT: Primary Discard Timer: Not Applicable or Implemented. Hardwired to 0.
7
0h
RO
FB2BEN: Fast Back-to-Back Enable: Not Applicable or Implemented. Hardwired to 0.
6
0h
RW
SRESET: Secondary Bus Reset: Setting this bit triggers a hot reset on the
corresponding PCI Express Port. This will force the LTSSM to transition to the Hot
Reset state (via Recovery) from L0, L0s, or L1 states.
5
0h
RO
MAMODE: Master Abort Mode: Does not apply to PCI Express. Hardwired to 0.
4
0h
RW
VGA16D: VGA 16-bit Decode: Enables the PCI-to-PCI bridge to provide 16-bit
decoding of VGA I/O address precluding the decoding of alias addresses every 1 KB.
This bit only has meaning if bit 3 (VGA Enable) of this register is also set to 1, enabling
VGA I/O decoding and forwarding by the bridge.
0: Execute 10-bit address decodes on VGA I/O accesses.
1: Execute 16-bit address decodes on VGA I/O accesses.
3
0h
RW
VGAEN: VGA Enable: Controls the routing of Processor initiated transactions targeting
VGA compatible I/O and memory address ranges. See the VGAEN/MDAP table in
device 0, offset 97h[0].
2
0h
RW
ISAEN: ISA Enable: Needed to exclude legacy resource decode to route ISA resources
to legacy decode path. Modifies the response by the root port to an I/O access issued
by the Processor that target ISA I/O addresses. This applies only to I/O addresses that
are enabled by the IOBASE and IOLIMIT registers.
0: All addresses defined by the IOBASE and IOLIMIT for Processor I/O transactions
will be mapped to PCI Express-G.
1: The root port will not forward to PCI Express-G any I/O transactions addressing the
last 768 bytes in each 1KB block even if the addresses are within the range defined by
the IOBASE and IOLIMIT registers.
1
0h
RW
SERREN: SERR Enable:
0: No forwarding of error messages from secondary side to primary side that could
result in an SERR.
1: ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR message
when individually enabled by the Root Control register.
0
0h
RW
PEREN: Parity Error Response Enable: Controls whether or not the Master Data Parity
Error bit in the Secondary Status register is set when the root port receives across the
link (upstream) a Read Data Completion Poisoned TLP
0: Master Data Parity Error bit in Secondary Status register can NOT be set.
1: Master Data Parity Error bit in Secondary Status register CAN be set.