Specification Sheet

Datasheet, Volume 2 of 2 493
PCI Express* Controller (x4) Registers
14.23 Interrupt Pin (INTRPIN)—Offset 3Dh
This register specifies which interrupt pin this device uses.
Access Method
Default: 1h
14.24 Bridge Control (BCTRL)—Offset 3Eh
This register provides extensions to the PCICMD register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (i.e. PCI
Express-G) as well as some bits that affect the overall behavior of the "virtual" Host-
PCI Express bridge embedded within the CPU, e.g. VGA compatible address ranges
mapping.
Access Method
Default: 0h
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:2] + 3Dh
7 4 0
0 0 0 0 0 0 0 1
INTPINH
INTPIN
Bit
Range
Default &
Access
Field Name (ID): Description
7:3
0h
RO
INTPINH: Interrupt Pin High:
2:0
1h
RW_O
INTPIN: Interrupt Pin: As a multifunction device, the PCI Express device may specify
any INTx (x=A,B,C,D) as its interrupt pin.
The Interrupt Pin register tells which interrupt pin the device (or device function) uses.
A value of 1 corresponds to INTA# (Default)
A value of 2 corresponds to INTB#
A value of 3 corresponds to INTC#
A value of 4 corresponds to INTD#
Devices (or device functions) that do not use an interrupt pin should put a 0 in this
register.
The values 05h through FFh are reserved.
This register is write once. BIOS should set this register to select the INTx to be used
by this root port.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:2] + 3Eh