Specification Sheet

PCI Express* Controller (x4) Registers
492 Datasheet, Volume 2 of 2
14.21 Capabilities Pointer (CAPPTR)—Offset 34h
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
Access Method
Default: 88h
14.22 Interrupt Line (INTRLINE)—Offset 3Ch
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
Access Method
Default: 0h
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:2] + 34h
7 4 0
1 0 0 0 1 0 0 0
CAPPTR1
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
88h
RO
CAPPTR1: First Capability: The first capability in the list is the Subsystem ID and
Subsystem Vendor ID Capability.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:2] + 3Ch
7 4 0
0 0 0 0 0 0 0 0
INTCON
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0h
RW
INTCON: Interrupt Connection: Used to communicate interrupt line routing
information.
BIOS Requirement: POST software writes the routing information into this register
as it initializes and configures the system. The value indicates to which input of the
system interrupt controller this device's interrupt pin is connected.