Specification Sheet

Datasheet, Volume 2 of 2 491
PCI Express* Controller (x4) Registers
14.20 Prefetchable Memory Limit Address Upper
(PMLIMITU)—Offset 2Ch
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Limit Address register
controls the Processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 39-bit address. The lower 7 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 39-bit address. This register
should be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1MB aligned memory block.
Note that prefetchable memory range is supported to allow segregation by the
configuration software between the memory ranges that should be defined as UC and
the ones that can be designated as a USWC (i.e. prefetchable) from the Processor
perspective.
Access Method
Default: 0h
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:2] + 2Ch
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PMLIMITU
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW
PMLIMITU: Prefetchable Memory Address Limit: Corresponds to A[63:32] of the
upper limit of the prefetchable Memory range that will be passed to PCI Express-G.