Specification Sheet

PCI Express* Controller (x4) Registers
490 Datasheet, Volume 2 of 2
14.19 Prefetchable Memory Base Address Upper
(PMBASEU)—Offset 28h
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Base Address register
controls the Processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 39-bit address. The lower 7 bits of the Upper Base Address register are
read/write and correspond to address bits A[38:32] of the 39-bit address. This register
should be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1MB boundary.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
15:4
0h
RW
PMLIMIT: Prefetchable Memory Address Limit: Corresponds to A[31:20] of the upper
limit of the address range passed to PCI Express-G.
3:0
1h
RO
AS64B: 64-bit Address Support: Indicates that the upper 32 bits of the prefetchable
memory region limit address are contained in the Prefetchable Memory Base Limit
Address register at 2Ch
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:2] + 28h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PMBASEU
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW
PMBASEU: Prefetchable Memory Base Address: Corresponds to A[63:32] of the lower
limit of the prefetchable memory range that will be passed to PCI Express-G.