Specification Sheet

Host Bridge/DRAM Registers

58 Datasheet, Volume 2 of 2

3 Host Bridge/DRAM Registers

Table 3-1. Summary of Bus: 0, Device: 0, Function: 0 (CFG)

Offset

Size

(Bytes)

0–1h 2 Vendor Identification (VID)—Offset 0h 8086h

2–3h 2 Device Identification (DID)—Offset 2h 59XXh

4–5h 2 PCI Command (PCICMD)—Offset 4h 6h

6–7h 2 PCI Status (PCISTS)—Offset 6h 90h

8–8h 1 Revision Identification (RID)—Offset 8h 0h

9–Bh 3 Class Code (CC)—Offset 9h 60000h

E–Eh 1 Header Type (HDR)—Offset Eh 0h

2C–2Dh 2 Subsystem Vendor Identification (SVID)—Offset 2Ch 0h

2E–2Fh 2 Subsystem Identification (SID)—Offset 2Eh 0h

34–34h 1 Capabilities Pointer (CAPPTR)—Offset 34h E0h

40–47h 8 PCI Express* Egress Port Base Address (PXPEPBAR)—Offset 40h 0h

48–4Fh 8 Host Memory Mapped Register Range Base (MCHBAR)—Offset 48h 0h

50–51h 2 GMCH Graphics Control Register (GGC)—Offset 50h 500h

54–57h 4 Device Enable (DEVEN)—Offset 54h 84BFh

58–5Bh 4 Protected Audio Video Path Control (PAVPC)—Offset 58h 0h

5C–5Fh 4 DMA Protected Range (DPR)—Offset 5Ch 0h

60–67h 8 PCI Express Register Range Base Address (PCIEXBAR)—Offset 60h 0h

68–6Fh 8 Root Complex Register Range Base Address (DMIBAR)—Offset 68h 0h

70–77h 8 Manageability Engine Base Address Register (MESEG)—Offset 70h 7FFFF00000h

78–7Fh 8 Manageability Engine Limit Address Register (MESEG)—Offset 78h 0h

80–80h 1 Programmable Attribute Map 0 (PAM0)—Offset 80h 0h

81–81h 1 Programmable Attribute Map 1 (PAM1)—Offset 81h 0h

82–82h 1 Programmable Attribute Map 2 (PAM2)—Offset 82h 0h

83–83h 1 Programmable Attribute Map 3 (PAM3)—Offset 83h 0h

84–84h 1 Programmable Attribute Map 4 (PAM4)—Offset 84h 0h

85–85h 1 Programmable Attribute Map 5 (PAM5)—Offset 85h 0h

86–86h 1 Programmable Attribute Map 6 (PAM6)—Offset 86h 0h

87–87h 1 Legacy Access Control (LAC)—Offset 87h 0h

88–88h 1 System Management RAM Control (SMRAMC)—Offset 88h 2h

90–97h 8 Remap Base Address Register (REMAPBASE)—Offset 90h 7FFFF00000h

98–9Fh 8 Remap Limit Address Register (REMAPLIMIT)—Offset 98h 0h

A0–A7h 8 Top of Memory (TOM)—Offset A0h 7FFFF00000h

A8–AFh 8

Top of Upper Usable DRAM (TOUUD)—Offset A8h 0h

B0–B3h 4 Base Data of Stolen Memory (BDSM)—Offset B0h 0h

B4–B7h 4 Base of GTT stolen Memory (BGSM)—Offset B4h 100000h