Specification Sheet

Datasheet, Volume 2 of 2 485
PCI Express* Controller (x4) Registers
Default: F0h
14.13 I/O Limit Address (IOLIMIT)—Offset 1Dh
This register controls the Processor to PCI Express-G I/O access routing based on the
following formula:
IO_BASE=< address =<IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be
at the top of a 4KB aligned address block.
Access Method
Default: 0h
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:2] + 1Ch
7 4 0
1 1 1 1 0 0 0 0
IOBASE
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
7:4
Fh
RW
IOBASE: I/O Address Base: Corresponds to A[15:12] of the I/O addresses passed by
the root port to PCI Express-G.
3:0
0h
RO
Reserved (RSVD): Reserved.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:2] + 1Dh
7 4 0
0 0 0 0 0 0 0 0
IOLIMIT
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
7:4
0h
RW
IOLIMIT: I/O Address Limit: Corresponds to A[15:12] of the I/O address limit of the
root port. Devices between this upper limit and IOBASE1 will be passed to the PCI
Express hierarchy associated with this device.
3:0
0h
RO
Reserved (RSVD): Reserved.