Specification Sheet

PCI Express* Controller (x4) Registers
482 Datasheet, Volume 2 of 2
14.7 Cache Line Size (CL)—Offset Ch
Access Method
Default: 0h
14.8 Header Type (HDR)—Offset Eh
This register identifies the header layout of the configuration space. No physical
register exists at this location.
Access Method
Default: 81h
2
3
2
0
1
6
1
2
8 4 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
BCC
SUBCC
PI
Bit
Range
Default &
Access
Field Name (ID): Description
23:16
6h
RO
BCC: Base Class Code: Indicates the base class code for this device. This code has the
value 06h, indicating a Bridge device.
15:8
4h
RO
SUBCC: Sub-Class Code: Indicates the sub-class code for this device. The code is 04h
indicating a PCI to PCI Bridge.
7:0
0h
RO
PI: Programming Interface: Indicates the programming interface of this device. This
value does not specify a particular register set layout and provides no practical use for
this device.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:2] + Ch
7 4 0
0 0 0 0 0 0 0 0
CLS
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0h
RW
CLS: Cache Line Size: Implemented by PCI Express devices as a read-write field for
legacy compatibility purposes but has no impact on any PCI Express device
functionality.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:2] + Eh