Specification Sheet

Datasheet, Volume 2 of 2 481
PCI Express* Controller (x4) Registers
14.5 Revision Identification (RID)—Offset 8h
This register contains the revision number of Device #1. These bits are read only and
writes to this register have no effect.
Access Method
Default: 0h
14.6 Class Code (CC)—Offset 9h
This register identifies the basic function of the device, a more specific sub-class, and a
register- specific programming interface.
Access Method
Default: 60400h
4
1h
RO
CAPL: Capabilities List: Indicates that a capabilities list is present. Hardwired to 1.
3
0h
ROV
INTAS: INTx Status: Indicates that an interrupt message is pending internally to the
device. Only PME and Hot Plug sources feed into this status bit (not PCI INTA-INTD
assert and de-assert messages). The INTA Assertion Disable bit, PCICMD1[10], has no
effect on this bit.
Note that INTA emulation interrupts received across the link are not reflected in this
bit.
2:0
0h
RO
Reserved (RSVD): Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:2] + 8h
7 4 0
0 0 0 0 0 0 0 0
RID_MSB
RID
Bit
Range
Default &
Access
Field Name (ID): Description
7:4
0h
RO
RID_MSB: Revision Identification Number MSB: This is an 8-bit value that indicates
the revision identification number for the root port.
3:0
0h
RO
RID: Revision Identification Number: This is an 8-bit value that indicates the revision
identification number for the root port.
Type: CFG
(Size: 24 bits)
Offset: [B:0, D:1, F:2] + 9h