Specification Sheet

Datasheet, Volume 2 of 2 479
PCI Express* Controller (x4) Registers
14.4 PCI Status (PCISTS)—Offset 6h
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express bridge embedded within the Root port.
Access Method
Default: 10h
2
0h
RW
BME: Bus Master Enable: Bus Master Enable (BME): Controls the ability of the PEG
port to forward Memory Read/Write Requests in the upstream direction.
0: This device is prevented from making memory requests to its primary bus. Note
that according to PCI Specification, as MSI interrupt messages are in-band memory
writes, disabling the bus master enable bit prevents this device from generating MSI
interrupt messages or passing them from its secondary bus to its primary bus.
Upstream memory writes/reads, peer writes/reads, and MSIs will all be treated as
illegal cycles. Writes are aborted. Reads are aborted and will return Unsupported
Request status (or Master abort) in its completion packet.
1: This device is allowed to issue requests to its primary bus. Completions for
previously issued memory read requests on the primary bus will be issued when the
data is available. This bit does not affect forwarding of Completions from the primary
interface to the secondary interface.
1
0h
RW
MAE: Memory Access Enable:
0: All of device's memory space is disabled.
1: Enable the Memory and Pre-fetchable memory address ranges defined in the
MBASE, MLIMIT, PMBASE, and PMLIMIT registers.
0
0h
RW
IOAE: IO Access Enable:
0: All of device's I/O space is disabled.
1: Enable the I/O address range defined in the IOBASE, and IOLIMIT registers.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:2] + 6h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
DPE
SSE
RMAS
RTAS
STAS
DEVT
PMDPE
FB2B
RSVD
CAP66
CAPL
INTAS
RSVD