Specification Sheet

PCI Express* Controller (x4) Registers
476 Datasheet, Volume 2 of 2
A4–A7h 4 Device Capabilities (DCAP)—Offset A4h 8001h
A8–A9h 2 Device Control (DCTL)—Offset A8h 0h
AA–ABh 2 Device Status (DSTS)—Offset AAh 0h
ACh 2 Link Capability (LCAP)—Offset ACh 33486h
B0–B1h 2 Link Control (LCTL)—Offset B0h 0h
B2–B3h 2 Link Status (LSTS)—Offset B2h 1000h
B4–B7h 4 Slot Capabilities (SLOTCAP)—Offset B4h 40000h
B8–B9h 2 Slot Control (SLOTCTL)—Offset B8h 0h
BA–BBh 2 Slot Status (SLOTSTS)—Offset BAh 0h
BC–BFh 4 Root Control (RCTL)—Offset BCh 0h
C0–C3h 4 Root Status (RSTS)—Offset C0h 0h
C4–C7h 4 Device Capabilities 2 (DCAP2)—Offset C4h B80h
C8–C9h 2 Device Control 2 (DCTL2)—Offset C8h 0h
D0–D1h 2 Link Control 2 (LCTL2)—Offset D0h 3h
D2–D3h 2 Link Status 2 (LSTS2)—Offset D2h 0h
104–107h 4 Port VC Capability Register 1 (PVCCAP1)—Offset 104h 0h
108–10Bh 4 Port VC Capability Register 2 (PVCCAP2)—Offset 108h 0h
10C–10Dh 2 Port VC Control (PVCCTL)—Offset 10Ch 0h
110–113h 4 VC0 Resource Capability (VC0RCAP)—Offset 110h 1h
114–117h 4 VC0 Resource Control (VC0RCTL)—Offset 114h 800000FFh
11A–11Bh 2 VC0 Resource Status (VC0RSTS)—Offset 11Ah 2h
1C4–1C7h 4 PEG Uncorrectable Error Status—Offset 1C4h 0h
1C8–1CBh 4 PEG Uncorrectable Error Mask—Offset 1C8h 0h
1CC–1CFh 4 PEG Uncorrectable Error Mask—Offset 1C8h 0h
1D0–1D3h 4 PEG Correctable Error Status—Offset 1D0h 0h
1D4–1D7h 4 PEG Correctable Error Mask—Offset 1D4h 0h
1D8–1DBh 4 PEG Advanced Error Capabilities and Control—Offset 1D8h 0h
1DC–1DFh 4
PEG Header Log—Offset 1DCh, 1E0h, 1E4h, 1E8h
0h
1E0–1E3h 4 0h
1E4–1E7h 4 0h
1E8–1EBh 4 0h
1EC–1EFh 4 PEG Root Error Command—Offset 1ECh 0h
1F0–1F3h 4 PEG Root Error Status—Offset 1F0h 0h
1F4–1F7h 4 PEG Error Source Identification—Offset 1F4h 0h
Table 14-1. Summary of Bus: 0, Device: 1, Function: 2 (CFG) (Continued)
Offset
Size
(Bytes)
Register Name (Register Symbol)
Default
Value