Specification Sheet

Datasheet, Volume 2 of 2 467
PCI Express* Controller (x8) Registers
13.54 VC0 Resource Control (VC0RCTL)—Offset 114h
Controls the resources associated with PCI Express Virtual Channel 0.
Access Method
Default: 800000FFh
15
0h
RO
RSNPT: Reject Snoop Transactions: Reject Snoop Transactions (RSNPT):
0: Transactions with or without the No Snoop bit set within the TLP header are
allowed on this VC.
1: When Set, any transaction for which the No Snoop attribute is applicable but is not
Set within the TLP Header will be rejected as an Unsupported Request
14:8
0h
RO
Reserved (RSVD): Reserved.
7:0
1h
RO
PAC: Port Arbitration Capability: Port Arbitration Capability - Indicates types of Port
Arbitration supported by the VC resource. This field is valid for all Switch Ports, Root
Ports that support peer-to-peer traffic, and RCRBs, but not for PCI Express Endpoint
devices or Root Ports that do not support peer to peer traffic.
Each bit location within this field corresponds to a Port Arbitration Capability defined
below. When more than one bit in this field is Set, it indicates that the VC resource can
be configured to provide different arbitration services.
Software selects among these capabilities by writing to the Port Arbitration Select field
(see below).
Defined bit positions are:
Bit 0 Non-configurable hardware-fixed arbitration scheme, e.g., Round Robin (RR)
Bit 1 Weighted Round Robin (WRR) arbitration with 32 phases
Bit 2 WRR arbitration with 64 phases
Bit 3 WRR arbitration with 128 phases
Bit 4 Time-based WRR with 128 phases
Bit 5 WRR arbitration with 256 phases
Bits 6-7Reserved
Processor only supported arbitration indicates "Non-configurable hardware-fixed
arbitration scheme".
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:1] + 114h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
VC0E
RSVD
VC0ID
RSVD
PAS
RSVD
TCHVC0M
TCVC0M
TC0VC0M