Specification Sheet

Processor Configuration Register Definitions and Address Ranges
54 Datasheet, Volume 2 of 2
The same registers control mapping of VGA I/O address ranges. The VGA I/O range is
defined as addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh
(inclusive of ISA address aliases – A[15:10] are not decoded). The function and
interaction of these two bits is described below.
MDA Present (MDAP): This bit works with the VGA Enable bit in the BCTRL register of
Device 1 to control the routing of processor-initiated transactions targeting MDA
compatible I/O and memory address ranges. This bit should not be set when the VGA
Enable bit is not set. If the VGA enable bit is set, accesses to I/O address range x3BCh
– x3BFh are forwarded to the DMI Interface. If the VGA enable bit is not set, accesses
to I/O address range x3BCh – x3BFh are treated just like any other I/O accesses; that
is, the cycles are forwarded to PCI Express if the address is within IOBASE and IOLIMIT
and the ISA enable bit is not set; otherwise, the accesses are forwarded to the DMI
Interface. MDA resources are defined as the following:
Any I/O reference that includes the I/O locations listed above, or their aliases, will be
forwarded to the DMI interface even if the reference includes I/O locations not listed
above.
For I/O reads that are split into multiple DWord accesses, this decode applies to each
DWord independently. For example, a read to x3B3h and x3B4h (quadword read to
x3B0h with BE#=E7h) will result in a DWord read from PEG at 3B0h (BE#=Eh), and a
DWord read from DMI at 3B4h (BE=7h). Since the processor will not issue I/O writes
crossing the DWord boundary, this case does not exist for writes.
Summary of decode priority:
• Processor Graphics VGA, if enabled, gets:
— 03C0h – 03CFh: always
— 03B0h – 03BBh: if MSR[0]=0 (MSR is I/O register 03C2h)
— 03D0h – 03DFh: if MSR[0]=1
NOTE: 03BCh – 03BFh never decodes to Processor Graphics; 3BCh – 3BEh are
parallel port I/Os, and 3BFh is only used by true MDA devices.
• Else, if MDA Present (if VGA on PEG is enabled), DMI gets:
— x3B4,5,8,9,A,F (any access with any of these bytes enabled, regardless of the
other BEs)
• Else, if VGA on PEG is enabled, PEG gets:
— x3B0h – x3BBh
— x3C0h – x3CFh
— x3D0h – x3DFh
• Else, if ISA Enable=1, DMI gets:
— upper 768 bytes of each 1K block
• Else, IOBASE/IOLIMIT apply.
Table 2-8. MDA Resources
Range Type Address
Memory 0B0000h – 0B7FFFh
I/O 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh (Including ISA address aliases, A[15:10] are not used
in decode)