Specification Sheet

Datasheet, Volume 2 of 2 463
PCI Express* Controller (x8) Registers
13.49 Link Status 2 (LSTS2)—Offset D2h
Access Method
Default: 0h
5
0h
RWS
HASD: Hardware Autonomous Speed Disable: When set to 1b this bit disables
hardware from changing the link speed for reasons other than attempting to correct
unreliable link operation by reducing link speed.
4
0h
RWS
EC: Enter Compliance: Software is permitted to force a link to enter Compliance mode
at the speed indicated in the Target Link Speed field by setting this bit to 1b in both
components on a link and then initiating a hot reset on the link.
3:0
3h
RWS
TLS: Target Link Speed: For Downstream Ports, this field sets an upper limit on Link
operational speed by restricting the values advertised by the Upstream component in
its training sequences. The encoding is the binary value of the bit in the Supported
Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the desired
target Link speed. All other encodings are reserved. For example, 5.0 GT/s
corresponds to bit 2 in the Supported Link Speeds Vector, so the encoding for a 5.0
GT/s target Link speed in this field is 0010b.
If a value is written to this field that does not correspond to a supported speed (as
indicated by the Max Link Speed Vector), the result is undefined. The default value of
this field is the highest Link speed supported by the component (as reported in the
Max Link Speed field of the Link Capabilities register) unless the corresponding
platform/form factor requires a different defaul value. For both Upstream and
Downstream Ports, this field is used to set the target compliance mode speed when
software is using the Enter Compliance bit to force a Link into compliance mode. For a
Multi-Function device associated with an Upstream Port, the field in Function 0 is of
type RWS, and only Function 0 controls the components Link behavior. In all other
Functions of that device, this field is of type RsvdP.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:1] + D2h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
LNKEQREQ
EQPH3SUCC EQPH2SUCC EQPH1SUCC
EQCOMPLETE
CURDELVL
Bit
Range
Default &
Access
Field Name (ID): Description
15:6
0h
RO
Reserved (RSVD): Reserved.
5
0h
RW1C
LNKEQREQ: This bit is Set by hardware to
request the Link equalization process to be performed on the
Link.
4
0h
ROV
EQPH3SUCC: Equalization Phase 3 Successful When set to 1b, this bit
indicates that Phase 3 of the Transmitter Equalization procedure
has successfully completed.
3
0h
ROV
EQPH2SUCC: Equalization Phase 2 Successful When set to 1b, this bit
indicates that Phase 2 of the Transmitter Equalization procedure
has successfully completed.