Specification Sheet

Datasheet, Volume 2 of 2 459
PCI Express* Controller (x8) Registers
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
0h
RO
Reserved (RSVD): Reserved.
19:18
0h
RW_O
OBFF_SUPPORTED: OBFF Supported
00b: OBFF Not Supported
01b: OBFF supported using Message signaling only
10b: OBFF supported using WAKE# signaling only
11b: OBFF supported using WAKE# and Message signaling
The value reported in this field should indicate support for WAKE#
signaling only if:
• for a Downstream Port, driving the WAKE# signal for OBFF is supported and the
connector or component connected Downstream is known to receive that same
WAKE# signal
• for an Upstream Port, receiving the WAKE# signal for OBFF is supported and, if
the component is on an add-in-card, that the component is connected to the
WAKE# signal on the connector.
Root Ports, Switch Ports, and Endpoints are permitted to implement this capability.
For a multi-Function device associated with an Upstream Port, each Function should
report the same value for this field.
For Bridges and Ports that do not implement this capability, this
field should be hardwired to 00b.
17:12
0h
RO
Reserved (RSVD): Reserved.
11
1h
RO
LTRS: Latency Tolerance and BW reporting Mechanism Supported: A value of 1b
indicates support for the optional Latency Tolerance & Bandwidth Requirement
Reporting (LTBWR) mechanism capability.
Root Ports, Switches and Endpoints are permitted to implement this capability. For
Switches that implement LTBWR, this bit should be set only at the upstream port.
For a multi-Function device, each Function should report the same value for this bit.
For Bridges, Downstream Ports, and components that do not implement this capability,
this bit should be hardwired to 0b.
10
0h
RO
Reserved (RSVD): Reserved.
9
1h
RO
ATOMIC128SUP: 128-bit CAS atomic operation completion support. This bit should
be set to 1b if the Function supports this optional capability.
8
1h
RO
ATOMIC64SUP: 64-bit atomic operation completion support. Includes FetchAdd,
Swap, and CAS AtomicOps. This bit should be set to 1b if the Function supports this
optional capability.
7
1h
RO
ATOMIC32SUP: 32-bit atomic operation completion support. Includes FetchAdd,
Swap, and CAS AtomicOps. This bit should be set to 1b if the Function supports this
optional capability.
6
0h
RO
ATOMIC_OP_ROUTING_SUPPORT: Atomic Operation Routing Supported. If set
then atomic operations are supported.