Specification Sheet
Datasheet, Volume 2 of 2 457
PCI Express* Controller (x8) Registers
13.45 Root Status (RSTS)—Offset C0h
Provides information about PCI Express Root Complex specific parameters.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:5
0h
RO
Reserved (RSVD): Reserved.
4
0h
RO
CSVE: Reserved for CRS Software Visibility Enable: This bit, when set, enables the
Root Port to return Configuration Request Retry Status (CRS) Completion Status to
software.
Root Ports that do not implement this capability should hardwire this bit to 0b.
3
0h
RW
PMEIE: PME Interrupt Enable:
0: No interrupts are generated as a result of receiving PME messages.
1: Enables interrupt generation upon receipt of a PME message as reflected in the
PME Status bit of the Root Status Register. A PME interrupt is also generated if the PME
Status bit of the Root Status Register is set when this bit is set from a cleared state.
If the bit change from 1 to 0 and interrupt is pending than interrupt is de-asserted
2
0h
RW
SEFEE: System Error on Fatal Error Enable: Controls the Root Complex's response to
fatal errors.
0: No SERR generated on receipt of fatal error.
1: Indicates that an SERR should be generated if a fatal error is reported by any of
the devices in the hierarchy associated with this Root Port, or by the Root Port itself.
1
0h
RW
SENFUEE: System Error on Non-Fatal Uncorrectable Error Enable: Controls the Root
Complex's response to non-fatal errors.
0: No SERR generated on receipt of non-fatal error.
1: Indicates that an SERR should be generated if a non-fatal error is reported by any
of the devices in the hierarchy associated with this Root Port, or by the Root Port itself.
0
0h
RW
SECEE: System Error on Correctable Error Enable: Controls the Root Complex's
response to correctable errors.
0: No SERR generated on receipt of correctable error.
1: Indicates that an SERR should be generated if a correctable error is reported by
any of the devices in the hierarchy associated with this Root Port, or by the Root Port
itself.
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:1] + C0h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
PMEP
PMES
PMERID