Specification Sheet

PCI Express* Controller (x8) Registers
456 Datasheet, Volume 2 of 2
13.44 Root Control (RCTL)—Offset BCh
Allows control of PCI Express Root Complex specific parameters. The system error
control bits in this register determine if corresponding SERRs are generated when our
device detects an error (reported in this device's Device Status register) or when an
error message is received across the link. Reporting of SERR as controlled by these bits
takes precedence over the SERR Enable in the PCI Command Register.
Access Method
Default: 0h
4
0h
RO
CC: Reserved for Command Completed: If Command Completed notification is
supported (as indicated by No Command Completed Support field of Slot Capabilities
Register), this bit is set when a hot-plug command has completed and the Hot-Plug
Controller is ready to accept a subsequent command. The Command Completed status
bit is set as an indication to host software that the Hot-Plug Controller has processed
the previous command and is ready to receive the next command; it provides no
guarantee that the action corresponding to the command is complete.
If Command Completed notification is not supported, this bit should be hardwired to
0b.
3
0h
RW1C
PDC: Presence Detect Changed: --A pulse indication that the inband presence detect
state has changed
This bit is set when the value reported in Presence Detect State is changed.
2
0h
RO
MSC: Reserved for MRL Sensor Changed: If an MRL sensor is implemented, this bit is
set when a MRL Sensor state change is detected. If an MRL sensor is not implemented,
this bit should not be set.
1
0h
RO
PFD: Reserved for Power Fault Detected: If a Power Controller that supports power
fault detection is implemented, this bit is set when the Power Controller detects a
power fault at this slot. Note that, depending on hardware capability, it is possible that
a power fault can be detected at any time, independent of the Power Controller Control
setting or the occupancy of the slot. If power fault detection is not supported, this bit
should not be set.
0
0h
RO
ABP: Reserved for Attention Button Pressed: If an Attention Button is implemented,
this bit is set when the attention button is pressed. If an Attention Button is not
supported, this bit should not be set.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:1] + BCh
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
CSVE
PMEIE
SEFEE
SENFUEE
SECEE