Specification Sheet

Datasheet, Volume 2 of 2 53
Processor Configuration Register Definitions and Address Ranges
Note: Additional qualification within Processor Graphics comprehends internal MDA support.
The VGA and MDA enabling bits detailed below control ranges not mapped to Processor
Graphics.
For regions mapped outside of the Processor Graphics (or if Processor Graphics is
disabled), the legacy VGA memory range A0000h – BFFFFh are mapped to the DMI
Interface or PCI Express depending on the programming of the VGA Enable bit in the
BCTRL configuration register in the PEG configuration space, and the MDAPxx bits in
the Legacy Access Control (LAC) register in Device 0 configuration space. The same
register controls mapping VGA I/O address ranges. The VGA I/O range is defined as
addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of
ISA address aliases – A[15:10] are not decoded). The function and interaction of these
two bits is described below:
VGA Enable: Controls the routing of processor initiated transactions targeting VGA
compatible I/O and memory address ranges. When this bit is set, the following
processor accesses will be forwarded to the PCI Express:
• Memory accesses in the range 0A0000h to 0BFFFFh
• I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh
(including ISA address aliases – A[15:10] are not decoded)
When this bit is set to a "1":
• Forwarding of these accesses issued by the processor is independent of the I/O
address and memory address ranges defined by the previously defined base and
limit registers.
• Forwarding of these accesses is also independent of the settings of the ISA Enable
settings if this bit is "1".
• Accesses to I/O address range x3BCh – x3BFh are forwarded to the DMI Interface.
When this bit is set to a "0":
• Accesses to I/O address range x3BCh – x3BFh are treated like any other I/O
accesses; the cycles are forwarded to PCI Express if the address is within IOBASE
and IOLIMIT and ISA enable bit is not set. Otherwise, these accesses are forwarded
to the DMI interface.
• VGA compatible memory and I/O range accesses are not forwarded to PCI Express
but rather they are mapped to the DMI Interface, unless they are mapped to PCI
Express using I/O and memory range registers defined above (IOBASE, IOLIMIT)
The following table shows the behavior for all combinations of MDA and VGA.
Table 2-7. VGA and MDA IO Transaction Mapping
VGA_en MDAP Range Destination Exceptions / Notes
0 0 VGA, MDA DMI interface
0 1 Illegal Undefined behavior results
1 0 VGA PCI Express
1 1 VGA PCI Express
1 1 MDA DMI interface
x3BCh – x3BEh will also go to DMI
interface