Specification Sheet

Datasheet, Volume 2 of 2 451
PCI Express* Controller (x8) Registers
Bit
Range
Default &
Access
Field Name (ID): Description
15
0h
RW1C
LABWS: Link Autonomous Bandwidth Status: This bit is set to 1b by hardware to
indicate that hardware has autonomously changed link speed or width, without the
port transitioning through DL_Down status, for reasons other than to attempt to
correct unreliable link operation.
This bit should be set if the Physical Layer reports a speed or width change was
initiated by the downstream component that was indicated as an autonomous change.
14
0h
RW1C
LBWMS: Link Bandwidth Management Status: This bit is set to 1b by hardware to
indicate that either of the following has occurred without the port transitioning through
DL_Down status:
A link retraining initiated by a write of 1b to the Retrain Link bit has completed.
Note: This bit is Set following any write of 1b to the Retrain Link bit, including when
the Link is in the process of retraining for some other reason.
Hardware has autonomously changed link speed or width to attempt to correct
unreliable link operation, either through an LTSSM timeout or a higher level process
This bit should be set if the Physical Layer reports a speed or width change was
initiated by the downstream component that was not indicated as an autonomous
change.
13
0h
ROV
DLLLA: Data Link Layer Link Active (Optional): This bit indicates the status of the
Data Link Control and Management State Machine. It returns a 1b to indicate the
DL_Active state, 0b otherwise.
This bit should be implemented if the corresponding Data Link Layer Active Capability
bit is implemented. Otherwise, this bit should be hardwired to 0b.
12
1h
RO
SCC: Slot Clock Configuration:
0: The device uses an independent clock irrespective of the presence of a reference
on the connector.
1: The device uses the same physical reference clock that the platform provides on
the connector.
11
0h
RO
LTRN: Link Training: Indicates that the Physical Layer LTSSM is in the Configuration or
Recovery state, or that 1b was written to the Retrain Link bit but Link training has not
yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery
state once Link training is complete.
10
0h
RO
Reserved (RSVD): Reserved.
9:4
0h
RO
NLW: Negotiated Link Width: Indicates negotiated link width. This field is valid only
when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully
completed).
00h: Reserved
01h: X1
02h: X2
04h: X4
08h: X8
10h: X16
All other encodings are reserved.
3:0
0h
RO
CLS: Current Link Speed: This field indicates the negotiated Link speed of the given
PCI Express Link.
The encoding is the binary value of the bit location in the Supported Link Speeds
Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed.
For example, a value of 0010b in this field indicates that the current Link speed is that
corresponding to bit 2 in the Supported Link Speeds Vector, which is 5.0 GT/s.
The value in this field is undefined when the Link is not up.