Specification Sheet

PCI Express* Controller (x8) Registers
450 Datasheet, Volume 2 of 2
13.40 Link Status (LSTS)—Offset B2h
Indicates PCI Express link status.
Access Method
Default: 1000h
6
0h
RW
CCC: Common Clock Configuration:
0: Indicates that this component and the component at the opposite end of this Link
are operating with asynchronous reference clock.
1: Indicates that this component and the component at the opposite end of this Link
are operating with a distributed common reference clock.
The state of this bit affects the L0s Exit Latency reported in LCAP[14:12] and the
N_FTS value advertised during link training. See PEGL0SLAT at offset 22Ch.
5
0h
RO
RL: Retrain Link:
0: Normal operation.
1: Full Link retraining is initiated by directing the Physical Layer LTSSM from L0, L0s,
or L1 states to the Recovery state.
This bit always returns 0 when read. This bit is cleared automatically (no need to write
a 0).
4
0h
RW
LD: Link Disable:
0: Normal operation
1: Link is disabled. Forces the LTSSM to transition to the Disabled state (via Recovery)
from L0, L0s, or L1 states. Link retraining happens automatically on 0 to 1 transition,
just like when coming out of reset.
Writes to this bit are immediately reflected in the value read from the bit, regardless of
actual Link state.
3
0h
RO
RCB: Read Completion Boundary: Hardwired to 0 to indicate 64 byte.
2
0h
RO
Reserved (RSVD): Reserved.
1:0
0h
RO
ASPM: Active State PM: Controls the level of active state power management
supported on the given link.
00: Disabled
01: L0s Entry Supported
10: L1 Entry Supported
11: L0s and L1 Entry Supported
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:1] + B2h
15 12 8 4 0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
LABWS
LBWMS
DLLLA
SCC
LTRN
RSVD
NLW
CLS