Specification Sheet

Datasheet, Volume 2 of 2 447
PCI Express* Controller (x8) Registers
13.38 Link Capability (LCAP)—Offset ACh
Indicates PCI link capabilities.
Access Method
Default: 33486h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
TP
RSVD
URD
FED
NFED
CED
Bit
Range
Default &
Access
Field Name (ID): Description
15:6
0h
RO
Reserved (RSVD): Reserved.
5
0h
RO
TP: Transactions Pending:
0: All pending transactions (including completions for any outstanding non-posted
requests on any used virtual channel) have been completed.
1: Indicates that the device has transaction(s) pending (including completions for any
outstanding non-posted requests for all used Traffic Classes).
Not Applicable or Implemented. Hardwired to 0.
4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RW1C
URD: Unsupported Request Detected: When set this bit indicates that the Device
received an Unsupported Request. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device Control Register.
Additionally, the Non-Fatal Error Detected bit or the Fatal Error Detected bit is set
according to the setting of the Unsupported Request Error Severity bit. In production
systems setting the Fatal Error Detected bit is not an option as support for AER will not
be reported.
2
0h
RW1C
FED: Fatal Error Detected: When set this bit indicates that fatal error(s) were
detected. Errors are logged in this register regardless of whether error reporting is
enabled or not in the Device Control register. When Advanced Error Handling is
enabled, errors are logged in this register regardless of the settings of the
uncorrectable error mask register.
1
0h
RW1C
NFED: Non-Fatal Error Detected: When set this bit indicates that non-fatal error(s)
were detected. Errors are logged in this register regardless of whether error reporting
is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this register regardless
of the settings of the uncorrectable error mask register.
0
0h
RW1C
CED: Correctable Error Detected: When set this bit indicates that correctable error(s)
were detected. Errors are logged in this register regardless of whether error reporting
is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this register regardless
of the settings of the correctable error mask register.
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:1] + ACh