Specification Sheet

PCI Express* Controller (x8) Registers
446 Datasheet, Volume 2 of 2
13.37 Device Status (DSTS)—Offset AAh
Reflects status corresponding to controls in the Device Control register. The error
reporting bits are in reference to errors detected by this device, not errors messages
received across the link.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
15
0h
RO
Reserved (RSVD): Reserved.
14:12
0h
RO
MRRS: Reserved for Max Read Request Size:
11
0h
RO
NSE: Reserved for Enable No Snoop:
10:8
0h
RO
Reserved (RSVD): Reserved.
7:5
0h
RW
MPS: Max Payload Size: 001:256B max supported payload for Transaction Layer
Packets (TLP).
As a receiver, the Device should handle TLPs as large as the set value; as transmitter,
the Device should not generate
TLPs exceeding the set value. BIOS should not set this field larger than the DCAP.MPS
of the DSD.
4
0h
RO
ROE: Reserved for Enable Relaxed Ordering:
3
0h
RW
URRE: Unsupported Request Reporting Enable: Unsupported Request Reporting
Enable (URRE): When set, allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_CORR
to the Root Control register when detecting an unmasked Unsupported Request (UR).
An ERR_CORR is signaled when an unmasked Advisory Non-Fatal UR is received. An
ERR_FATAL or ERR_NONFATAL is sent to the Root Control register when an
uncorrectable non-Advisory UR is received with the severity bit set in the
Uncorrectable Error Severity register.
2
0h
RW
FERE: Fatal Error Reporting Enable: Fatal Error Reporting Enable (FERE): When set,
enables signaling of ERR_FATAL to the Root Control register due to internally detected
errors or error messages received across the link. Other bits also control the full scope
of related error reporting.
1
0h
RW
NERE: Non-Fatal Error Reporting Enable: Non-Fatal Error Reporting Enable (NERE):
When set, enables signaling of ERR_NONFATAL to the Root Control register due to
internally detected errors or error messages received across the link. Other bits also
control the full scope of related error reporting.
0
0h
RW
CERE: Correctable Error Reporting Enable: Correctable Error Reporting Enable
(CERE): When set, enables signaling of ERR_CORR to the Root Control register due to
internally detected errors or error messages received across the link. Other bits also
control the full scope of related error reporting.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:1] + AAh