Specification Sheet

Processor Configuration Register Definitions and Address Ranges
52 Datasheet, Volume 2 of 2
• Processor Graphics VGA in Device 0 Function 0 is enabled through register GGC bit
1.
• Processor Graphics's memory accesses (PCICMD2 04h – 05h, MAE bit 1) in Device
2 configuration space are enabled.
• VGA compatibility memory accesses (VGA Miscellaneous Output register – MSR
Register, bit 1) are enabled.
• Software sets the proper value for VGA Memory Map Mode register (VGA GR06
Register, bits 3:2). See the following table for translations.
Note: Additional qualification within Processor Graphics comprehends internal MDA support.
The VGA and MDA enabling bits detailed below control segments not mapped to
Processor Graphics.
VGA I/O range is defined as addresses where A[15:0] are in the ranges 03B0h to
03BBh, and 03C0h to 03DFh. VGA I/O accesses are directed to Processor Graphics
depends on the following configuration:
• Processor Graphics controller in Device 2 is enabled through register DEVEN.D2EN
bit 4.
• Processor Graphics VGA in Device 0 Function 0 is enabled through register GGC bit
1.
• Processor Graphics's I/O accesses (PCICMD2 04 – 05h, IOAE bit 0) in Device 2 are
enabled.
• VGA I/O decodes for Processor Graphics uses 16 address bits (15:0) there is no
aliasing. This is different when compared to a bridge device (Device 1) that used
only 10 address bits (A 9:0) for VGA I/O decode.
• VGA I/O input/output address select (VGA Miscellaneous Output register - MSR
Register, bit 0) is used to select mapping of I/O access as defined in the following
table.
Table 2-5. Processor Graphics Frame Buffer Accesses
Memory Access
GR06(3:2)
A0000h - AFFFFh B0000h - B7FFFh MDA B8000h - BFFFFh
00 Processor Graphics Processor Graphics Processor Graphics
01
Processor Graphics PCI Express bridge or DMI
interface
PCI Express bridge or DMI
interface
10
PCI Express bridge or DMI
interface
Processor Graphics PCI Express bridge or DMI
interface
11
PCI Express bridge or DMI
interface
PCI Express bridge or DMI
interface
Processor Graphics
Table 2-6. Processor Graphics VGA I/O Mapping
I/O Access
MSRb0
3CX 3DX 3B0h – 3BBh 3BCh – 3BFh
0
Processor
Graphics
PCI Express bridge or
DMI interface
Processor Graphics
PCI Express bridge or DMI
interface
1
Processor
Graphics
Processor Graphics
PCI Express bridge or
DMI interface
PCI Express bridge or DMI
interface