Specification Sheet

Datasheet, Volume 2 of 2 445
PCI Express* Controller (x8) Registers
13.36 Device Control (DCTL)—Offset A8h
Provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
Access Method
Default: 0h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RSVD
RBER
RSVD
ETFS
PFS
MPS
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0h
RO
Reserved (RSVD): Reserved.
15
1h
RO
RBER: Role Based Error Reporting: Role Based Error Reporting (RBER): Indicates that
this device implements the functionality defined in the Error Reporting ECN as required
by the PCI Express 1.1 spec.
14:6
0h
RO
Reserved (RSVD): Reserved.
5
0h
RO
ETFS: Extended Tag Field Supported: Hardwired to indicate support for 5-bit Tags as a
Requestor.
4:3
0h
RO
PFS: Phantom Functions Supported: Not Applicable or Implemented. Hardwired to 0.
2:0
1h
RW_O
MPS: Max Payload Size: Default indicates 256B max supported payload for
Transaction Layer Packets (TLP).
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:1] + A8h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
MRRS
NSE
RSVD
MPS
ROE
URRE
FERE
NERE
CERE