Specification Sheet

Datasheet, Volume 2 of 2 51
Processor Configuration Register Definitions and Address Ranges
2.15 PCI Express* Interface Decode Rules
All "SNOOP semantic" PCI Express* transactions are kept coherent with processor
caches. All "Snoop not required semantic" cycles should reference the direct DRAM
address range. PCI Express non-snoop initiated cycles are not snooped. If a "Snoop not
required semantic" cycle is outside of the address range mapped to system memory,
then it will proceed as follows:
• Reads: Sent to DRAM address 000C_0000h (non-snooped) and will return
"unsuccessful completion".
• Writes: Sent to DRAM address 000C_0000h (non-snooped) with byte enables all
disabled Peer writes from PEG to DMI are not supported.
If PEG bus master enable is not set, all reads and writes are treated as unsupported
requests.
2.15.1 TC/VC Mapping Details
• VC0 (enabled by default)
— Snoop port and Non-snoop Asynchronous transactions are supported.
— Processor Graphics GMADR writes can occur. Unlike FSB chipsets, these will
NOT be snooped regardless of the snoop not required (SNR) bit.
— Processor Graphics GMADR reads (unsupported).
— Peer writes are only supported between PEG ports. PEG to DMI peer write
accesses are NOT supported.
— MSI can occur. These will route to the cores (IntLogical/IntPhysical) regardless
of the SNR bit.
• VC1 is not supported.
• VCm is not supported.
2.16 Legacy VGA and I/O Range Decode Rules
The legacy 128 KB VGA memory range 000A_0000h – 000B_FFFFh can be mapped to
Processor Graphics (Device 2), PCI Express (Device 1 Functions), and/or to the DMI
interface depending on the programming of the VGA steering bits. Priority for VGA
mapping is constant in that the processor always decodes internally mapped devices
first. Internal to the processor, decode precedence is always given to Processor
Graphics. The processor always positively decodes internally mapped devices, namely
the Processor Graphics. Subsequent decoding of regions mapped to either PCI Express
port or the DMI Interface depends on the Legacy VGA configurations bits (VGA Enable
and MDAP).
For the remainder of this section, PCI Express can refer to either the device 1 port
functions.
VGA range accesses will always be mapped as UC type memory.
Accesses to the VGA memory range are directed to Processor Graphics depend on the
configuration. The configuration is specified by:
• Processor Graphics controller in Device 2 is enabled (DEVEN.D2EN bit 4)