Specification Sheet

Datasheet, Volume 2 of 2 431
PCI Express* Controller (x8) Registers
13.18 Prefetchable Memory Limit Address (PMLIMIT)—
Offset 26h
This register in conjunction with the corresponding Upper Limit Address register
controls the Processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
should be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1MB aligned memory block. Note that prefetchable
memory range is supported to allow segregation by the configuration software between
the memory ranges that should be defined as UC and the ones that can be designated
as a USWC (i.e. prefetchable) from the Processor perspective.
Access Method
Default: 1h
15 12 8 4 0
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1
PMBASE
AS64
Bit
Range
Default &
Access
Field Name (ID): Description
15:4
FFFh
RW
PMBASE: Prefetchable Memory Base Address: Corresponds to A[31:20] of the lower
limit of the memory range that will be passed to PCI Express-G.
3:0
1h
RO
AS64: 64-bit Address Support: Indicates that the upper 32 bits of the prefetchable
memory region base address are contained in the Prefetchable Memory base Upper
Address register at 28h.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:1] + 26h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
PMLIMIT
AS64B