Specification Sheet

PCI Express* Controller (x8) Registers
430 Datasheet, Volume 2 of 2
in a true plug-and-play manner to the prefetchable address range for improved CPU-
PCI Express memory access performance.
Note also that configuration software is responsible for programming all address range
registers (prefetchable, non-prefetchable) with the values that provide exclusive
address ranges i.e. prevent overlap with each other and/or with the ranges covered
with the main memory. There is no provision in the Processor hardware to enforce
prevention of overlap and operations of the system in the case of overlap are not
guaranteed.
Access Method
Default: 0h
13.17 Prefetchable Memory Base Address (PMBASE)—
Offset 24h
This register in conjunction with the corresponding Upper Base Address register
controls the Processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
should be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1MB boundary.
Access Method
Default: FFF1h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:1] + 22h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MLIMIT
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
15:4
0h
RW
MLIMIT: Memory Address Limit: Corresponds to A[31:20] of the upper limit of the
address range passed to PCI Express-G.
3:0
0h
RO
Reserved (RSVD): Reserved.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:1] + 24h