Specification Sheet

PCI Express* Controller (x8) Registers
428 Datasheet, Volume 2 of 2
13.14 Secondary Status (SSTS)—Offset 1Eh
SSTS is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (i.e. PCI Express-G side) of the "virtual" PCI-PCI bridge
embedded within the processor.
Access Method
Default: 0h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:1] + 1Eh
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DPE
RSE
RMA
RTA
STA
DEVT
SMDPE
FB2B
RSVD
CAP66
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
15
0h
RW1C
DPE: Detected Parity Error: This bit is set by the Secondary Side for a Type 1
Configuration Space header device whenever it receives a Poisoned TLP, regardless of
the state of the Parity Error Response Enable bit in the Bridge Control Register.
14
0h
RW1C
RSE: Received System Error: This bit is set when the Secondary Side for a Type 1
configuration space header device receives an ERR_FATAL or ERR_NONFATAL.
13
0h
RW1C
RMA: Received Master Abort: This bit is set when the Secondary Side for Type 1
Configuration Space Header Device (for requests initiated by the Type 1 Header Device
itself) receives a Completion with Unsupported Request Completion Status.
12
0h
RW1C
RTA: Received Target Abort: This bit is set when the Secondary Side for Type 1
Configuration Space Header Device (for requests initiated by the Type 1 Header Device
itself) receives a Completion with Completer Abort Completion Status.
11
0h
RO
STA: Signaled Target Abort: Not Applicable or Implemented. Hardwired to 0. The
Processor does not generate Target Aborts (The root port will never complete a
request using the Completer Abort Completion status).
UR detected inside the Processor (such as in iMPH/MC will be reported in primary side
status)
10:9
0h
RO
DEVT: DEVSELB Timing: Not Applicable or Implemented. Hardwired to 0.
8
0h
RW1C
SMDPE: Master Data Parity Error: When set indicates that the Processor received
across the link (upstream) a Read Data Completion Poisoned TLP (EP=1). This bit can
only be set when the Parity Error Enable bit in the Bridge Control register is set.
7
0h
RO
FB2B: Fast Back-to-Back: Not Applicable or Implemented. Hardwired to 0.
6
0h
RO
Reserved (RSVD): Reserved.
5
0h
RO
CAP66: 66/60 MHz capability: Not Applicable or Implemented. Hardwired to 0.
4:0
0h
RO
Reserved (RSVD): Reserved.