Specification Sheet

4 Datasheet, Volume 2 of 2
3 Host Bridge/DRAM Registers .................................................................................. 46
3.1 Vendor Identification (VID)—Offset 0h ................................................................. 47
3.2 Device Identification (DID)—Offset 2h ................................................................. 48
3.3 PCI Command (PCICMD)—Offset 4h .................................................................... 48
3.4 PCI Status (PCISTS)—Offset 6h .......................................................................... 49
3.5 Revision Identification (RID)—Offset 8h ............................................................... 51
3.6 Class Code (CC)—Offset 9h ................................................................................ 51
3.7 Header Type (HDR)—Offset Eh ........................................................................... 52
3.8 Subsystem Vendor Identification (SVID)—Offset 2Ch ............................................. 53
3.9 Subsystem Identification (SID)—Offset 2Eh.......................................................... 53
3.10 Capabilities Pointer (CAPPTR)—Offset 34h ............................................................ 54
3.11 PCI Express* Egress Port Base Address (PXPEPBAR)—Offset 40h............................. 54
3.12 Host Memory Mapped Register Range Base (MCHBAR)—Offset 48h.......................... 55
3.13 GMCH Graphics Control Register (GGC)—Offset 50h .............................................. 56
3.14 Device Enable (DEVEN)—Offset 54h .................................................................... 57
3.15 Protected Audio Video Path Control (PAVPC)—Offset 58h........................................ 59
3.16 DMA Protected Range (DPR)—Offset 5Ch ............................................................. 61
3.17 PCI Express Register Range Base Address (PCIEXBAR)—Offset 60h ......................... 62
3.18 Root Complex Register Range Base Address (DMIBAR)—Offset 68h ......................... 63
3.19 Manageability Engine Base Address Register (MESEG)—Offset 70h .......................... 64
3.20 Manageability Engine Limit Address Register (MESEG)—Offset 78h .......................... 65
3.21 Programmable Attribute Map 0 (PAM0)—Offset 80h ............................................... 66
3.22 Programmable Attribute Map 1 (PAM1)—Offset 81h ............................................... 67
3.23 Programmable Attribute Map 2 (PAM2)—Offset 82h ............................................... 68
3.24 Programmable Attribute Map 3 (PAM3)—Offset 83h ............................................... 69
3.25 Programmable Attribute Map 4 (PAM4)—Offset 84h ............................................... 70
3.26 Programmable Attribute Map 5 (PAM5)—Offset 85h ............................................... 72
3.27 Programmable Attribute Map 6 (PAM6)—Offset 86h ............................................... 73
3.28 Legacy Access Control (LAC)—Offset 87h ............................................................. 74
3.29 System Management RAM Control (SMRAMC)—Offset 88h...................................... 77
3.30 Remap Base Address Register (REMAPBASE)—Offset 90h ....................................... 78
3.31 Remap Limit Address Register (REMAPLIMIT)—Offset 98h ...................................... 79
3.32 Top of Memory (TOM)—Offset A0h ...................................................................... 80
3.33 Top of Upper Usable DRAM (TOUUD)—Offset A8h.................................................. 80
3.34 Base Data of Stolen Memory (BDSM)—Offset B0h ................................................. 81
3.35 Base of GTT stolen Memory (BGSM)—Offset B4h................................................... 82
3.36 TSEG Memory Base (TSEGMB)—Offset B8h .......................................................... 83
3.37 Top of Low Usable DRAM (TOLUD)—Offset BCh ..................................................... 83
3.38 Scratchpad Data (SKPD)—Offset DCh .................................................................. 85
3.39 Capabilities A (CAPID0)—Offset E4h .................................................................... 85
3.40 Capabilities B (CAPID0)—Offset E8h .................................................................... 86
3.41 Capabilities C (CAPID0)—Offset ECh .................................................................... 88
4 Processor Graphics Registers .................................................................................. 89
4.1 Vendor Identification (VID2)—Offset 0h ............................................................... 90
4.2 Device Identification (DID2)—Offset 2h ............................................................... 90
4.3 PCI Command (PCICMD)—Offset 4h .................................................................... 91
4.4 PCI Status (PCISTS2)—Offset 6h ........................................................................ 92
4.5 Revision Identification (RID2)—Offset 8h ............................................................. 93
4.6 Class Code (CC)—Offset 9h ................................................................................ 94
4.7 Cache Line Size (CLS)—Offset Ch........................................................................ 94
4.8 Master Latency Timer (MLT2)—Offset Dh ............................................................. 95
4.9 Header Type (HDR2)—Offset Eh.......................................................................... 95
4.10 Graphics Translation Table, Memory Mapped
Range Address (GTTMMADR)—Offset 10h............................................................. 96