Specification Sheet

Datasheet, Volume 2 of 2 425
PCI Express* Controller (x8) Registers
13.9 Primary Bus Number (PBUSN)—Offset 18h
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
bus #0.
Access Method
Default: 0h
13.10 Secondary Bus Number (SBUSN)—Offset 19h
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge i.e. to PCI Express-G. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
Access Method
Default: 0h
7 4 0
1 0 0 0 0 0 0 1
HDR
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
81h
RO
HDR: Header Type Register: Device #1 returns 81 to indicate that this is a multi
function device with bridge header layout.
Device #6 returns 01 to indicate that this is a single function device with bridge
header layout.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:1] + 18h
7 4 0
0 0 0 0 0 0 0 0
BUSN
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0h
RO
BUSN: Primary Bus Number: Configuration software typically programs this field with
the number of the bus on the primary side of the bridge. Since the Processor root port
is an internal device and its primary bus is always 0, these bits are read only and are
hardwired to 0.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:1] + 19h