Specification Sheet

Datasheet, Volume 2 of 2 49
Processor Configuration Register Definitions and Address Ranges
2.14.2 Traffic Class (TC) / Virtual Channel (VC) Mapping Details
• VC0 (enabled by default)
— Snoop port and Non-snoop Asynchronous transactions are supported.
— Internal Graphics GMADR writes can occur. These writes will NOT be snooped
regardless of the snoop not required (SNR) bit.
— Processor Graphics GMADR reads (unsupported).
— Peer writes can occur. The SNR bit is ignored.
— MSI can occur. These will route and be sent to the cores as Intlogical/
IntPhysical interrupts regardless of the SNR bit.
— VLW messages can occur. These will route and be sent to the cores as VLW
messages regardless of the SNR bit.
— MCTP messages can occur. These are routed in a peer fashion.
• VC1 (Optionally enabled)
— Supports non-snoop transactions only. (Used for isochronous traffic). The PCI
Express* Egress port (PXPEPBAR) should also be programmed appropriately.
— The snoop not required (SNR) bit should be set. Any transaction with the SNR
bit not set will be treated as an unsupported request.
— MSI and peer transactions are treated as unsupported requests.
— No "pacer" arbitration or TWRR arbitration will occur. Never remaps to different
port. (PCH takes care of Egress port remapping). The PCH meters TCm Intel ME
accesses and Intel
®
High Definition Audio (Intel
®
HD Audio) TC1 access
bandwidth.
— Processor Graphics GMADR writes and GMADR reads are not supported.
• VCm accesses
— VCm access only map to Intel ME stolen DRAM. These transactions carry the
direct physical DRAM address (no redirection or remapping of any kind will
occur). This is how the PCH Intel ME accesses its dedicated DRAM stolen space.
— DMI block will decode these transactions to ensure only Intel ME stolen
memory is targeted, and abort otherwise.
— VCm transactions will only route non-snoop.
— VCm transactions will not go through VTd remap tables.
— The remapbase/remaplimit registers to not apply to VCm transactions.