Specification Sheet

Datasheet, Volume 2 of 2 415
PCI Express* Controller (x16) Registers
12.63 PEG Root Error Command—Offset 1ECh
The Root Error Command register allows further control of Root Complex response to
Correctable, Non-Fatal, and Fatal error Messages. Bit fields enable or disable generation
of interrupts in addition to Do_SERR VDM sent to PCH.
Access Method
Type: CFG Offset: [B:0, D:1, F:0] + 1ECh
(Size: 32 bits)
Default: 0h
12.64 PEG Root Error Status—Offset 1F0h
The Root Error Status register reports status of error messages received by the root
complex, and of errors detected by the Root Port itself (which are treated conceptually
as if the Root Port had sent an error message to itself). This register is updated
regardless of the settings of the Root Control register and the Root Error Command
register (which is not even implemented).
When an error is received by the Root Complex, the respective error received bit is set
which indicates that a particular error category occurred. Software may clear an error
status by writing a 1 to the respective bit.
Access Method
Type: CFG Offset: [B:0, D:1, F:0] + 1F0h
(Size: 32 bits)
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:3 0h RW Reserved (RSVD): Reserved.
2 0h RW FERE:
Fatal Error Reporting Enable
1 0h RW NFERE: Non-Fatal Error Reporting Enable
0 0h RW CERE: Correctable Error Reporting Enable
Bit
Range
Default &
Access
Field Name (ID): Description
31:27 0h RO AEIMN: Reserved for Advanced Error Interrupt Message Number:
26:7 0h RW1CS Reserved (RSVD): Reserved.
6 0h RW1CS FEMR: Fatal Error Messages Received:
5 0h RW1CS NFEMR: Non-Fatal Error Messages Received:
4 0h RW1CS FUF: First Uncorrectable Fatal:
3 0h RW1CS MEFNR: Multiple ERR_FATAL/NONFATAL Received: