Specification Sheet

PCI Express* Controller (x16) Registers
414 Datasheet, Volume 2 of 2
12.61 PEG Advanced Error Capabilities and Control—
Offset 1D8h
The PCI Express Advanced Error Reporting (AER) capabilities defined through this
register. First Error is logged here.
Access Method
Type: CFG Offset: [B:0, D:1, F:0] + 1D8h
(Size: 32 bits)
Default: 0h
12.62 PEG Header Log—Offset 1DCh, 1E0h, 1E4h, 1E8h
The PCI Express Advanced Error Reporting (AER) capability for header logging will use
this register for a header log.
Note: This description refers to all Header Log registers (HL0-HL3).
Access Method
Type: CFG Offset: [B:0, D:1, F:0] + 1DCh/1E0h/1E4h/1E8h
(Size: 32 bits)
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:11 0h RO Reserved (RSVD): Reserved.
10 0h RO MHRE: Multiple Header Recording Enable
9 0h RO MHRC: Multiple Header Recording Capable
8 0h RO ECRCCE: ECRC Check Enable
7 0h RO ECRCCC: ECRC Check Capable
6 0h RO ECRCGE: ECRC Generation Enable
5 0h R0 ECRCGC: ECRC Generation Capable
4:0 0h ROS FEP: First Error Pointer
Bit
Range
Default &
Access
Field Name (ID): Description
31:0 0h ROS HTAE: Header of TLP Associated with Error