Specification Sheet

PCI Express* Controller (x16) Registers
412 Datasheet, Volume 2 of 2
12.58 PEG Uncorrectable Error Severity—Offset 1CCh
Controls whether an individual error is reported as a non-fatal or fatal error. An error is
reported as fatal when the corresponding error bit in the severity register is set. If the
bit is cleared, the corresponding error is considered nonfatal. This register is for test
and debug purposes only.
Access Method
Type: CFG Offset: [B:0, D:1, F:0] + 1CCh
(Size: 32 bits)
Default: 0h
12.59 PEG Correctable Error Status—Offset 1D0h
Reports error status of individual error sources on a PCI Express device. An individual
error status bit that is set indicates that a particular error occurred. Software may clear
an error status by writing a 1 to the respective bit. This register is for test and debug
purposes only.
Note: Corner cases exist where bogus errors can get logged in this register on the L0 to
Recovery transition where TS1 packets could be flagged as errors.
Access Method
Type: CFG Offset: [B:0, D:1, F:0] + 1D0h
(Size: 32 bits)
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:21 0h RWS Reserved (RSVD): Reserved.
20 0h RWS URES:
Unsupported Request Error Severity
19 0h RO ECRCES: Reserved for ECRC Error Severity
18 0h RWS MTLPS: Malformed TLP Severity
17 0h RWS ROS: Receiver Overflow Severity
16 0h RWS UCS: Unexpected Completion Severity
15 0h RO CAS: Reserved for Completer Abort Severity
14 0h RWS CTS: Completion Timeout Severity
13 0h RO FCPES: Reserved for Flow Control Protocol Error Severity
12 0h RWS PTLPSEV: Poisoned TLP Severity
11:5 0h RWS Reserved (RSVD): Reserved.
4 0h RWS DLPES: Data Link Protocol Error Severity
3:0 0h RWS Reserved (RSVD): Reserved.