Specification Sheet

Datasheet, Volume 2 of 2 411
PCI Express* Controller (x16) Registers
12.57 PEG Uncorrectable Error Mask—Offset 1C8h
Controls reporting of individual errors by the device (or logic associated with this port)
to the PCI Express Root Complex. As these errors are not originating on the other side
of a PCI Express link, no PCI Express error message is sent, but the unmasked error is
reported directly to the root control logic. A masked error (respective bit set to 1 in the
mask register) has no action taken. There is a mask bit per error bit of the
Uncorrectable Error Status register. This register is for test and debug purposes only.
Access Method
Type: CFG Offset: [B:0, D:1, F:0] + 1C8h
(Size: 32 bits)
Default: 0h
11:5 0h RW1CS Reserved (RSVD): Reserved.
4 0h RW1CS DLPES: Data Link Protocol Error Status: The Data Link Layer Protocol Error that
causes this bit to be set will also cause the Fatal Error Detected bit in Device
Status[2] to be set if not already set.
3:0 0h RW1CS Reserved (RSVD): Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description
Bit
Range
Default &
Access
Field Name (ID): Description
31:21 0h RWS Reserved (RSVD): Reserved.
20 0h RWS UREM:
Unsupported Request Error Mask
19 0h RO ECRCEM: Reserved for ECRC Error Mask
18 0h RWS MTLPM: Malformed TLP Mask
17 0h RWS ROM: Receiver Overflow Mask
16 0h RWS UCM: Unexpected Completion Mask
15 0h RO CAM: Reserved for Completer Abort Mask
14 0h RWS CTM: Completion Timeout Mask
13 0h RO FCPEM: Reserved for Flow Control Protocol Error Mask
12 0h RWS PTLPM: Poisoned TLP Mask
11:5 0h RWS Reserved (RSVD): Reserved.
4 0h RWS DLPEM: Data Link Protocol Error Mask
3:0 0h RWS Reserved (RSVD): Reserved.