Specification Sheet

PCI Express* Controller (x16) Registers
410 Datasheet, Volume 2 of 2
12.56 PEG Uncorrectable Error Status—Offset 1C4h
Reports error status of individual error sources on a PCI Express device. An individual
error status bit that is set indicates that a particular error occurred. Error status is
cleared by writing a 1 to the respective bit. This register is for test and debug purposes
only.
Access Method
Type: CFG Offset: [B:0, D:1, F:0] + 1C4h
(Size: 32 bits)
Default: 0h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RSVD
VC0NP
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
15:2
0h
RO
Reserved (RSVD): Reserved.
1
1h
RO_V
VC0NP: VC0 Negotiation Pending:
0: The VC negotiation is complete.
1: The VC resource is still in the process of negotiation (initialization or disabling).
This bit indicates the status of the process of Flow Control initialization. It is set by
default on Reset, as well as whenever the corresponding Virtual Channel is Disabled or
the Link is in the DL_Down state. It is cleared when the link successfully exits the
FC_INIT2 state.
Before using a Virtual Channel, software should check whether the VC Negotiation
Pending fields for that Virtual Channel are cleared in both Components on a Link.
0
0h
RO
Reserved (RSVD): Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description
31:21 0h RW1CS Reserved (RSVD): Reserved.
20 0h RW1CS URES:
Unsupported Request Error Status
19 0h RO ECRCES: Reserved for ECRC Error Status
18 0h RW1CS MTLPS: Malformed TLP Status
17 0h RW1CS ROS: Receiver Overflow Status
16 0h RW1CS UCS: Unexpected Completion Status
15 0h RO CAS: Reserved for Completer Abort Status
14 0h RW1CS CTS: Completion Timeout Status
13 0h RO FCPES: Reserved for Flow Control Protocol Error Status
12 0h RW1CS PTLPS: Poisoned TLP Status