Specification Sheet

Processor Configuration Register Definitions and Address Ranges
48 Datasheet, Volume 2 of 2
2.14 Direct Media Interface (DMI) Interface Decode
Rules
All "SNOOP semantic" PCI Express* transactions are kept coherent with processor
caches.
All "Snoop not required semantic" cycles reference the main DRAM address range. PCI
Express non-snoop initiated cycles are not snooped.
The processor accepts accesses from the DMI Interface to the following address
ranges:
• All snoop memory read and write accesses to Main DRAM including PAM region
(except stolen memory ranges, TSEG, A0000h – BFFFFh space)
• Write accesses to enabled VGA range, MBASE/MLIMIT, and PMBASE/PMLIMIT will
be routed as peer cycles to the PCI Express interface.
• Write accesses above the top of usable DRAM and below 4 GB (not decoding to PCI
Express or GMADR space) will be treated as master aborts.
• Read accesses above the top of usable DRAM and below 4 GB (not decoding to PCI
Express) will be treated as unsupported requests.
• Reads and accesses above the TOUUD will be treated as unsupported requests on
VC0.
DMI Interface memory read accesses that fall between TOLUD and 4 GB are considered
invalid and will master abort. These invalid read accesses will be reassigned to address
000C_0000h and dispatch to DRAM. Reads will return unsupported request completion.
Writes targeting PCI Express space will be treated as peer-to-peer cycles.
There is a known usage model for peer writes from DMI to PEG. A video capture card
can be plugged into the PCH PCI bus. The video capture card can send video capture
data (writes) directly into the frame buffer on an external graphics card (writes to the
PEG port). As a result, peer writes from DMI to PEG should be supported.
I/O cycles and configuration cycles are not supported in the upstream direction. The
result will be an unsupported request completion status.
2.14.1 DMI Accesses to the Processor that Cross Device
Boundaries
The processor does not support transactions that cross device boundaries. This should
not occur because PCI Express transactions are not allowed to cross a 4 KB boundary.
For reads, the processor will provide separate completion status for each naturally-
aligned 64-byte block or, if chaining is enabled, each 128-byte block. If the starting
address of a transaction hits a valid address, the portion of a request that hits that
target device (PCI Express or DRAM) will complete normally.
If the starting transaction address hits an invalid address, the entire transaction will be
remapped to address 000C_0000h and dispatched to DRAM. A single unsupported
request completion will result.