Specification Sheet

Datasheet, Volume 2 of 2 405
PCI Express* Controller (x16) Registers
12.50 Port VC Capability Register 1 (PVCCAP1)—Offset
104h
Describes the configuration of PCI Express Virtual Channels associated with this port.
Access Method
Default: 0h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
LNKEQREQ
EQPH3SUCC EQPH2SUCC EQPH1SUCC
EQCOMPLETE
CURDELVL
Bit
Range
Default &
Access
Field Name (ID): Description
15:6
0h
RO
Reserved (RSVD): Reserved.
5
0h
RW1C
LNKEQREQ: This bit is Set by hardware to
request the Link equalization process to be performed on the
Link.
4
0h
ROV
EQPH3SUCC: Equalization Phase 3 Successful When set to 1b, this bit
indicates that Phase 3 of the Transmitter Equalization procedure
has successfully completed.
3
0h
ROV
EQPH2SUCC: Equalization Phase 2 Successful When set to 1b, this bit
indicates that Phase 2 of the Transmitter Equalization procedure
has successfully completed.
2
0h
ROV
EQPH1SUCC: Equalization Phase 1 Successful When set to 1b, this bit
indicates that Phase 1 of the Transmitter Equalization procedure
has successfully completed.
1
0h
ROV
EQCOMPLETE: Equalization Complete When set to 1b, this bit indicates that
the Transmitter Equalization procedure has completed.
0
0h
RO
CURDELVL: Current De-emphasis Level: Current De-emphasis Level - When the Link
is operating at 5 GT/s speed, this reflects the level of de-emphasis.
Encodings:
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s speed, this bit is 0b.
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:0] + 104h