Specification Sheet
Datasheet, Volume 2 of 2 403
PCI Express* Controller (x16) Registers
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
ComplianceDeemphasis
compsos
entermodcompliance
txmargin
selectabledeemphasis
HASD
EC
TLS
Bit
Range
Default &
Access
Field Name (ID): Description
15:12
0h
RWS
ComplianceDeemphasis: Compliance De-emphasis: For 8 GT/s Data Rate: This field
sets the Transmitter Preset level in Polling.Compliance state if the entry occurred due
to the Enter Compliance bit being 1b.
This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred
due to the Enter Compliance bit being 1b.
Defined encodings are:
0001b -3.5 dB
0000b -6 dB
When the Link is operating at 2.5 GT/s, the setting of this bit has no effect.
Components that support only 2.5 GT/s speed are permitted to hardwire this bit to 0b.
For a Multi-Function device associated with an Upstream Port, the bit in Function 0 is
of type RWS, and only Function 0 controls the component's Link behavior. In all other
Functions of that device, this bit is of type RsvdP.
The default value of this bit is 0000b.
This bit is intended for debug, compliance testing purposes. System firmware and
software is allowed to modify this bit only during debug or compliance testing.
11
0h
RWS
compsos: Compliance SOS: When set to 1b, the LTSSM is required to send SKP
Ordered Sets periodically in between the (modified) compliance patterns.
For a Multi-Function device associated with an Upstream Port, the bit in Function 0 is
of type RWS, and only Function 0 controls the component's Link behavior. In all other
Functions of that device, this bit is of type RsvdP.
The default value of this bit is 0b.
This bit is applicable when the Link is operating at 2.5 GT/s or 5 GT/s data rates only.
Components that support only the 2.5 GT/s speed are permitted to hardwire this field
to 0b.
10
0h
RWS
entermodcompliance: Enter Modified Compliance: When this bit is set to 1b, the
device transmits modified compliance pattern if the LTSSM enters Polling.Compliance
state.
Components that support only the 2.5GT/s speed are permitted to hardwire this bit to
0b.
Default value of this field is 0b.