Specification Sheet
PCI Express* Controller (x16) Registers
402 Datasheet, Volume 2 of 2
12.48 Link Control 2 (LCTL2)—Offset D0h
Access Method
Default: 3h
Bit
Range
Default &
Access
Field Name (ID): Description
15
0h
RO
Reserved (RSVD): Reserved.
14:13
0h
RW
OBFFEN: Reserved.
12:11
0h
RO
Reserved (RSVD): Reserved.
10
0h
RW_V
LTREN: Latency Tolerance Reporting Mechanism Enable: When Set to 1b, this bit
enables the Latency Tolerance & Reporting (LTR) mechanism.
This bit is required for all Functions that support the LTR Capability. For a Multi-
Function device associated with an upstream port of a device that implements LTBWR,
the bit in Function 0 is of type RW, and only Function 0 controls the components Link
behavior. In all other Functions of that device, this bit is of type RsvdP.
Components that do not implement LTR are permitted to hardwire this bit to 0b.
Default value of this bit is 0b.
This bit is cleared when the port goes to DL_down state. HW ignores the value of this
bit.
9:7
0h
RO
Reserved (RSVD): Reserved.
6
0h
RO
ATOMIC_OP_REQUESTER_EN: AtomicOp Requester Enable Applicable only to
Endpoints and Root Ports; should be hardwired to 0b for other Function types. The
Function is allowed to initiate AtomicOp Requests only if this bit and the Bus Master
Enable bit in the Command register are both Set.
This bit is required to be RW if the Endpoint or Root Port is capable of initiating
AtomicOp Requests, but otherwise is permitted to be hardwired to 0b.
This bit does not serve as a capability bit. This bit is permitted to be RW even if no
AtomicOp Requester capabilities are supported by the Endpoint or Root Port.
5
0h
RW
ARIFEN: ARI Forward Enable: When set, the Downstream Port disables its traditional
Device Number field being 0 enforcement when turning a Type 1 Configuration
Request into a Type 0 Configuration Request, permitting access to Extended Functions
in an ARI Device immediately below the Port.
Default value of this bit is 0b. should be hardwired to 0b if the ARI Forwarding
Supported bit is 0b.
4:0
0h
RO
Reserved (RSVD): Reserved.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:0] + D0h