Specification Sheet

Datasheet, Volume 2 of 2 397
PCI Express* Controller (x16) Registers
6
0h
ROV
PDS: Presence Detect State: --In band presence detect state:
0: Slot Empty
1: Card present in slot
This bit indicates the presence of an adapter in the slot, reflected by the logical "OR" of
the Physical Layer in-band presence detect mechanism and, if present, any out-of-
band presence detect mechanism defined for the slot's corresponding form factor.
Note that the in-band presence detect mechanism requires that power be applied to
an adapter for its presence to be detected. Consequently, form factors that require a
power controller for hot-plug should implement a physical pin presence detect
mechanism.
Defined encodings are:
0: Slot Empty
1: Card Present in slot
This register should be implemented on all Downstream Ports that implement slots.
For Downstream Ports not connected to slots (where the Slot Implemented bit of the
PCI Express Capabilities Register is 0b), this bit should return 1b.
5
0h
RO
MSS: Reserved for MRL Sensor State: This register reports the status of the MRL
sensor if it is implemented.
Defined encodings are:
0: MRL Closed
1: MRL Open
4
0h
RO
CC: Reserved for Command Completed: If Command Completed notification is
supported (as indicated by No Command Completed Support field of Slot Capabilities
Register), this bit is set when a hot-plug command has completed and the Hot-Plug
Controller is ready to accept a subsequent command. The Command Completed status
bit is set as an indication to host software that the Hot-Plug Controller has processed
the previous command and is ready to receive the next command; it provides no
guarantee that the action corresponding to the command is complete.
If Command Completed notification is not supported, this bit should be hardwired to
0b.
3
0h
RW1C
PDC: Presence Detect Changed: --A pulse indication that the inband presence detect
state has changed
This bit is set when the value reported in Presence Detect State is changed.
2
0h
RO
MSC: Reserved for MRL Sensor Changed: If an MRL sensor is implemented, this bit is
set when a MRL Sensor state change is detected. If an MRL sensor is not implemented,
this bit should not be set.
1
0h
RO
PFD: Reserved for Power Fault Detected: If a Power Controller that supports power
fault detection is implemented, this bit is set when the Power Controller detects a
power fault at this slot. Note that, depending on hardware capability, it is possible that
a power fault can be detected at any time, independent of the Power Controller Control
setting or the occupancy of the slot. If power fault detection is not supported, this bit
should not be set.
0
0h
RO
ABP: Reserved for Attention Button Pressed: If an Attention Button is implemented,
this bit is set when the attention button is pressed. If an Attention Button is not
supported, this bit should not be set.
Bit
Range
Default &
Access
Field Name (ID): Description