Specification Sheet

PCI Express* Controller (x16) Registers
396 Datasheet, Volume 2 of 2
12.43 Slot Status (SLOTSTS)—Offset BAh
PCI Express Slot related registers.
Access Method
Default: 0h
2
0h
RO
MSCE: Reserved for MRL Sensor Changed Enable: When set to 1b, this bit enables
software notification on a MRL sensor changed event.
Default value of this field is 0b. If the MRL Sensor Present field in the Slot Capabilities
register is set to 0b, this bit is permitted to be read-only with a value of 0b.
1
0h
RO
PFDE: Reserved for Power Fault Detected Enable: When set to 1b, this bit enables
software notification on a power fault event.
Default value of this field is 0b. If Power Fault detection is not supported, this bit is
permitted to be read-only with a value of 0b
0
0h
RO
ABPE: Reserved for Attention Button Pressed Enable: When set to 1b, this bit enables
software notification on an attention button pressed event.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:0] + BAh
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
DLLSC
EIS
PDS
MSS
CC
PDC
MSC
PFD
ABP
Bit
Range
Default &
Access
Field Name (ID): Description
15:9
0h
RO
Reserved (RSVD): Reserved.
8
0h
RO
DLLSC: Reserved for Data Link Layer State Changed: This bit is set when the value
reported in the Data Link Layer Link Active field of the Link Status register is changed.
In response to a Data Link Layer State Changed event, software should read the Data
Link Layer Link Active field of the Link Status register to determine if the link is active
before initiating configuration cycles to the hot plugged device.
7
0h
RO
EIS: Reserved for Electromechanical Interlock Status: If an Electromechanical
Interlock is implemented, this bit indicates the current status of the Electromechanical
Interlock.
Defined encodings are:
0: Electromechanical Interlock Disengaged
1: Electromechanical Interlock Engaged