Specification Sheet

Datasheet, Volume 2 of 2 47
Processor Configuration Register Definitions and Address Ranges
A set of I/O accesses are consumed by the Processor Graphics device if it is enabled.
The mechanisms for Processor Graphics I/O decode and the associated control is
explained in following sub-sections.
The I/O accesses are forwarded normally to the DMI Interface bus unless they fall
within the PCI Express I/O address range as defined by the mechanisms explained
below. I/O writes are NOT posted. Memory writes to PCH or PCI Express are posted.
The PCI Express devices have a register that can disable the routing of I/O cycles to the
PCI Express device.
The processor responds to I/O cycles initiated on PCI Express or DMI with an UR status.
Upstream I/O cycles and configuration cycles should never occur. If one does occur, the
transaction will complete with an UR completion status.
I/O reads that lie within 8-byte boundaries but cross 4-byte boundaries are issued from
the processor as one transaction. The reads will be split into two separate transactions.
I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries will be split
into two transactions by the processor.
2.13.1 PCI Express* I/O Address Mapping
The processor can be programmed to direct non-memory (I/O) accesses to the PCI
Express bus interface when processor initiated I/O cycle addresses are within the PCI
Express I/O address range. This range is controlled using the I/O Base Address
(IOBASE) and I/O Limit Address (IOLIMIT) registers in Device 1 Functions 0, 1, 2
configuration space.
Address decoding for this range is based on the following concept. The top 4 bits of the
respective I/O Base and I/O Limit registers correspond to address bits A[15:12] of an
I/O address. For the purpose of address decoding, the device assumes that the lower
12 address bits A[11:0] of the I/O base are zero and that address bits A[11:0] of the I/
O limit address are FFFh. This forces the I/O address range alignment to a 4 KB
boundary and produces a size granularity of 4 KB.
The processor positively decodes I/O accesses to PCI Express I/O address space as
defined by the following equation:
I/O_Base_Address ≤ processor I/O Cycle Address ≤ I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration
software and it depends on the size of I/O space claimed by the PCI Express device.
The processor also forwards accesses to the Legacy VGA I/O ranges according to the
settings in the PEG configuration registers BCTRL (VGA Enable) and PCICMD (IOAE),
unless a second adapter (monochrome) is present on the DMI Interface/PCI (or ISA).
The presence of a second graphics adapter is determined by the MDAP configuration
bit. When MDAP is set to 1, the processor will decode legacy monochrome I/O ranges
and forward them to the DMI Interface. The I/O ranges decoded for the monochrome
adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh.
The PEG I/O address range registers defined above are used for all I/O space allocation
for any devices requiring such a window on PCI-Express.
The PCICMD register can disable the routing of I/O cycles to PCI Express.