Specification Sheet

PCI Express* Controller (x16) Registers
394 Datasheet, Volume 2 of 2
12.42 Slot Control (SLOTCTL)—Offset B8h
PCI Express Slot related registers allow for the support of Hot Plug.
Access Method
Default: 0h
2
0h
RO
MSP: Reserved for MRL Sensor Present: When set to 1b, this bit indicates that an MRL
Sensor is implemented on the chassis for this slot.
1
0h
RO
PCP: Reserved for Power Controller Present: When set to 1b, this bit indicates that a
software programmable Power Controller is implemented for this slot/adapter
(depending on form factor).
0
0h
RO
ABP: Reserved for Attention Button Present: When set to 1b, this bit indicates that an
Attention Button for this slot is electrically controlled by the chassis.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:0] + B8h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
DLLSCE
EIC
PCC
PIC
AIC
HPIE
CCI
PDCE
MSCE
PFDE
ABPE
Bit
Range
Default &
Access
Field Name (ID): Description
15:13
0h
RO
Reserved (RSVD): Reserved.
12
0h
RO
DLLSCE: Reserved for Data Link Layer State Changed Enable: Reserved for Data Link
Layer State Changed Enable (DLLSCE):
If the Data Link Layer Link Active capability is implemented, when set to 1b, this field
enables software notification when Data Link Layer Link Active field is changed.
If the Data Link Layer Link Active capability is not implemented, this bit is permitted to
be read-only with a value of 0b.
11
0h
RO
EIC: Reserved for Electromechanical Interlock Control: If an Electromechanical
Interlock is implemented, a write of 1b to this field causes the state of the interlock to
toggle. A write of 0b to this field has no effect. A read to this register always returns a
0.