Specification Sheet

Datasheet, Volume 2 of 2 389
PCI Express* Controller (x16) Registers
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 0
RSVD
ASPM Optionality Compliance
RSVD
L1 Exit Latency
L0s Exit Latency
Active State Link PM Support
MLW
MLS
Bit
Range
Default &
Access
Field Name (ID): Description
31:23
0h
RO
Reserved (RSVD): Reserved.
22
0h
RO
ASPM Optionality Compliance: This bit should be set to 1b in all Functions.
Components implemented against certain earlier versions of this specification will have
this bit set to 0b. Software is permitted to use the value of this bit to help determine
whether to enable ASPM or whether to run ASPM compliance tests.
21:18
0h
RO
Reserved (RSVD): Reserved.
17:15
3h
RW_O
L1 Exit Latency: Indicates the length of time this Port requires to complete the
transition from L1 to L0. The value 010 b indicates the range of 2 us to less than 4 us.
Both bytes of this register that contain a portion of this field should be written
simultaneously in order to prevent an intermediate (and undesired) value from ever
existing.
14:12
4h
RO
L0s Exit Latency: Indicates the length of time this Port requires to complete the
transition from L0s to L0.
000: Less than 64 ns
001: 64ns to less than 128ns
010: 128ns to less than 256 ns
011: 256ns to less than 512ns
100: 512ns to less than 1us
101: 1 us to less than 2 us
110: 2 us - 4 us
111: More than 4 us
11:10
3h
RW_O
Active State Link PM Support: Root port supports ASPM L0s and L1.
9:4
10h
RW_OV
Max Link Width (MLW): Indicates the maximum number of lanes supported for this
link.
3:0
3h
RW_OV
Max Link Speed (MLS): The encoding is the binary value of the bit location in the
Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to
the maximum Link speed. For example, a value of 0010b in this field indicates that the
maximum Link speed is that corresponding to bit 2 in the Supported Link Speeds
Vector, which is 5.0 GT/s.