Specification Sheet

Processor Configuration Register Definitions and Address Ranges
46 Datasheet, Volume 2 of 2
2.11 SMM and VGA Access Through GTT TLB
Accesses through GTT TLB address translation SMM DRAM space are not allowed.
Writes will be routed to memory address 000C_0000h with byte enables de-asserted
and reads will be routed to Memory address 000C_0000h. If a GTT TLB translated
address hits SMM DRAM space, an error is recorded.
PCI Express* and DMI Interface originated accesses are never allowed to access SMM
space directly or through the GTT TLB address translation. If a GTT TLB translated
address hits enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface write accesses through the GMADR range will not be
snooped. Only PCI Express and DMI assesses to GMADR linear range (defined using
fence registers) are supported. PCI Express and DMI Interface tileY and tileX writes to
GMADR are not supported. If, when translated, the resulting physical address is to
enable SMM DRAM space, the request will be remapped to address 000C_0000h with
de-asserted byte enables.
PCI Express and DMI Interface read accesses to the GMADR range are not supported.
Therefore, there are no address translation concerns. PCI Express and DMI Interface
reads to GMADR will be remapped to address 000C_0000h. The read will complete with
UR (unsupported request) completion status.
GTT fetches are always decoded (at fetch time) to ensure fetch is not in SMM (actually,
anything above base of TSEG or 640 KB - 1 MB). Thus, the fetches will be invalid and
go to address 000C_0000h. This is not specific to PCI Express or DMI; it also applies to
processor or Processor Graphics engines.
2.12 Intel
®
Management Engine (Intel
®
ME) Stolen
Memory Accesses
There are two ways to validly access Intel ME stolen memory:
• PCH accesses mapped to VCm will be decoded to ensure only Intel ME stolen
memory is targeted. These VCm accesses will route non-snooped directly to DRAM.
This is the means by which the Intel ME (located within the PCH) is able to access
the Intel ME stolen range.
• The display engine is allowed to access Intel ME stolen memory as part of Intel
®
KVM technology flows. Specifically, display-initiated HHP reads (for displaying a
Intel KVM technology frame) and display initiated LP non-snoop writes (for display
writing an Intel KVM technology captured frame) to Intel ME stolen memory are
allowed.
2.13 I/O Address Space
The system agent generates either DMI Interface or PCI Express* bus cycles for all
processor I/O accesses that it does not claim. The Configuration Address Register
(CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA) are used to
generate PCI configuration space access.
The processor allows 64K+3 bytes to be addressed within the I/O space. The upper 3
locations can be accessed only during I/O address wrap-around.