Specification Sheet

Datasheet, Volume 2 of 2 385
PCI Express* Controller (x16) Registers
12.34 PCI Express-G Capabilities (PEG)—Offset A2h
Indicates PCI Express device capabilities.
Access Method
Default: 142h
12.35 Device Capabilities (DCAP)—Offset A4h
Indicates PCI Express device capabilities.
Access Method
Default: 8001h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:0] + A2h
15 12 8 4 0
0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0
RSVD
IMN
SI
DPT
PCIECV
Bit
Range
Default &
Access
Field Name (ID): Description
15:14
0h
RO
Reserved (RSVD): Reserved.
13:9
0h
RO
IMN: Interrupt Message Number: Not Applicable or Implemented. Hardwired to 0.
8
1h
RW_O
SI: Slot Implemented:
0: The PCI Express Link associated with this port is connected to an integrated
component or is disabled.
1: The PCI Express Link associated with this port is connected to a slot.
BIOS Requirement: This field should be initialized appropriately if a slot connection
is not implemented.
7:4
4h
RO
DPT: Device/Port Type: Hardwired to 4h to indicate root port of PCI Express Root
Complex.
3:0
2h
RO
PCIECV: PCI Express Capability Version: PCI Express Capability Version (PCIECV):
Hardwired to 2h to indicate compliance to the PCI Express Capabilities Register
Expansion ECN.
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:0] + A4h